Agilent Technologies Enters Final
PALO ALTO Palo Alto, city, California
Palo Alto (p city (1990 pop. 55,900), Santa Clara co., W Calif.; inc. 1894. Although primarily residential, Palo Alto has aerospace, electronics, and advanced research industries. , Calif. -- Versatest V5500 Optimizes Single-Insertion Testing of MCPs with Multiple Memory Types for Industry-Leading Tester Utilization, Higher Throughput
Agilent Technologies This text needs sources or references that come in reliable, third-party publications. Alone, primary sources and sources connected with the main topics this particular article commonly are not sufficient to have accurate encyclopedia article. Inc. (NYSE NYSE
See: London stock exchange :A) today introduced the Versatest Series Model V5500, the original cost-effective final test solution for multichip package devices (MCP (1) See Microsoft certification.
(2) (MultiChip Package) A chip package that contains a couple of chips. It is actually essentially a multichip module (MCM) that utilizes a laminated, printed-circuit-board-like substrate (MCM-L) other than ceramic (MCM-C). ) and discrete flash memory. The Versatest V5500's tester-per-site architecture and optional Programmable Interface Matrix optimize single-insertion testing of MCPs with multiple memory types (Flash, DRAM and SRAM See static RAM.
SRAM - static random-access memory ). This causes industry-leading tester utilization and higher throughput, dramatically lowering cost-of-test.
With 16,384 pins per testhead, the V5500 with Programmable Interface Matrix may be the highest pin-count tester for final test today. The V5500's high pin count was created to make full use of today's leading-edge x320 handlers at nearly 320 NAND (Not AND) A Boolean logic operation that maybe true if any single input is false. Two-input NAND gates in many cases are used since the sole logic element on gate array chips, because all Boolean operations can be created from NAND gates. See flash memory. devices in parallel, and it enables parallel testing of high-pin-count NOR and MCPs at up to 256 devices in parallel.
"The Versatest V5500 brings 16,384 pins to the table -- dramatically a lot more than any competitor generally offer," said Gayn Erickson, vice chairman in Agilent's memory test division. "It radically reduces cost-of-test by getting both high-parallel and single-insertion testing of MCPs. Particularly with the Matrix, this new solution presents an important factor technology for enabling the industry's massive adoption of complex MCPs, which are usually essential to the wide alternative of 3G phones in addition to other advanced electronics market applications."
Nothing else tester available for sale are able to do high-parallel test of complex MCPs accompanied by a single insertion. The Versatest V5500 lowers capital expense and test time through optimized single-insertion test of MCP memories. Single-insertion test requires high I/O (Input/Output) The transfer of strategy between your mcm 財布 CPU along with a peripheral device. Every transfer is an output within one unit and a port to another one. See PC input/output.
I/O - Input/Output pin count testers additionally, the capacity mcm リュック fully test all memory devices present on the MCP; it ought to accommodate different pin, power, speed and accuracy requirements of each and every memory die. Other testers, optimized for the single variety of memory die, or without worrying about performance to use lots of the ルイヴィトン バッグ memories within the stack, force additional insertions on two or more testers, driving up capital and consumable costs consumable cost Administration Those necessary expenses borne via the lab or another hospital service together with reagents, disposables, along with supplies, together with maintenance and lease contracts. See Disposables. and reducing yield.
When testing MCPs, each die is tested serially. Thus a little subset with the total I/O pins essential to test the high-pin-count MCP is commonly employed to examine every individual die. Compared to other testers, resource utilization is low because the majority within the expensive, full I/O hardware instructed to satisfy the MCP's pin count sits idle.
Agilent's new resource-switching Matrix technology paired with the V5500's tester-per-site architecture has the industry's lowest cost-of-test for MCPs by enabling an optimal combination of 100 percent-utilized tester resources and full capability test all memory types. The V5500 with Matrix's industry-highest 16,384 pins per testhead clarifies that it's your only solution perfect for testing complex MCPs, with as many as 256 pins, at 64 to 256 devices in parallel.
The V5500 with Matrix also addresses the requirement for testing discrete memories, providing a high-parallel, low-cost-of-test solution for NOR and NAND devices. In high-parallel test mode the Matrix offers a 4X surge in parallelism An overlapping of processing, input/output (I/O) or both.
1. parallelism - parallel processing.
2. (parallel) parallelism - The highest level group of ルイヴィトン 財布 independent subtasks with a given task from a given point in its execution. when testing Flash. High-pin-count NOR can be tested at as much 256 devices in parallel. NAND could be tested at up to ルイヴィトン 320 in parallel with today's leading-edge x320 handlers.
Agilent's Versatest memory test products present an end-to-end solution (jargon) end-to-end solution - (E2ES) A term that implies that the supplier of the application program or system will supply many of the hardware and/or software components and resouces based on mcm バッグ the customer's requirement rarely are other supplier need be involved.
Compare: turn-key solution. , from engineering development to high-volume manufacturing both for wafer sort and final test.
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